Title :
Optimized NH3 annealing Process for high-quality HfSiON gate oxide
Author :
Akbar, Mohammad S. ; Cho, H.-J. ; Choi, Rino ; Kang, C.S. ; Kang, C.Y. ; Choi, C.H. ; Rhee, S.J. ; Kim, Y.H. ; Lee, Jack C.
Author_Institution :
Microelectron. Res. Center, Univ. of Texas, Austin, TX, USA
fDate :
7/1/2004 12:00:00 AM
Abstract :
Optimization of fabrication process in obtaining high-quality HfSiON gate-oxide metal-oxide semiconductor field-effect transistors (MOSFETs) by NH3 post-deposition anneal (PDA) has been performed. At 600°C anneal temperature, a longer anneal duration resulted in reduced leakage current density (J), reduced trapped charges, and lower hysteresis in capacitance-voltage curves, but with a slight increase in effective oxide thickness (EOT). Subsequent interfacial layer growth with longer anneal duration was attributed to the increase in EOT. MOSFET, fabricated by the optimized process of 600°C, 40 s NH3 PDA, showed superior Id--Vd (drain current-drain voltage) and charge-trapping characteristics as compared to control Hf-Silicate.
Keywords :
MOSFET; annealing; hafnium compounds; nitrogen compounds; semiconductor growth; 600 C; Hatband voltage; Hf-silicate; HfSiON; NH3; effective oxide thickness; fabrication optimization; gate oxide; hysteresis; interfacial layer growth; leakage current density; metal-oxide semiconductor field-effect transistors; optimized annealing process; postdeposition anneal; trapped charges; Annealing; Capacitance-voltage characteristics; FETs; Fabrication; Hysteresis; Leakage current; MOS devices; MOSFETs; Temperature; Voltage control; Charge trap; EOT; Hf-Silicate; HfSiON; effective oxide thickness; flatband voltage; hysteresis;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2004.830270
