• DocumentCode
    1017290
  • Title

    A hierarchical computer architecture for distributed simulation

  • Author

    Concepcion, Arturo I.

  • Author_Institution
    Coll. of Comput. Studies, De La Salle Univ., Manila, Philippines
  • Volume
    38
  • Issue
    2
  • fYear
    1989
  • fDate
    2/1/1989 12:00:00 AM
  • Firstpage
    311
  • Lastpage
    319
  • Abstract
    A methodology is developed to map hierarchical, modular discrete-event models onto a distributed simulated architecture, the hierarchical multibus multiprocessor architecture (HM2A). The proposed architecture contains features closely reflecting the structure, behaviour, and modular properties of the model being simulated. Hence, this approach improves on previous approaches, which impose the model on a predesigned architecture
  • Keywords
    computer architecture; distributed processing; multiprocessing systems; distributed simulation; hierarchical computer architecture; hierarchical multibus multiprocessor architecture; modular discrete-event models; Computational modeling; Computer architecture; Computer simulation; Delay; Discrete event simulation; Fault tolerance; Pipeline processing; Switches; Systolic arrays; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.16512
  • Filename
    16512
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1017290