Title :
Processor equivalence for daisy chain load sharing processors
Author :
Robertazzi, Thomas G.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
fDate :
10/1/1993 12:00:00 AM
Abstract :
A linear daisy chain of processors in which processor load is divisible and shared among the processors is examined. It is shown that two or more processors can be collapsed into a single equivalent processor. This equivalence allows a characterization of the nature of the minimal time solution, a simple method to determine when to distribute load for linear daisy chain networks of processors without front end communication subprocessors and closed form expressions for the equivalent processing speed of infinitely large daisy chains of processors
Keywords :
parallel architectures; daisy chain load sharing processors; equivalent processors; minimal time solution; Computer architecture; Computer networks; Concurrent computing; Delay; Multiprocessor interconnection networks; Parallel machines; Parallel processing; Processor scheduling; Terrorism; Timing;
Journal_Title :
Aerospace and Electronic Systems, IEEE Transactions on
