Title :
High SCR design for one-transistor split-gate full-featured EEPROM
Author :
Chu, Wen-Ting ; Lin, Hao-Hsiung ; Yu-Hsiung Wang ; Hsieh, Chia-Ta ; Sung, Hung-Cheng ; Lin, Yung-Tao ; Wang, Yu-Hsiung
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
7/1/2004 12:00:00 AM
Abstract :
A high source-coupling ratio design for full-featured EEPROM composed of one-transistor split-gate cells with a cell area of less than 22 F2 is proposed. This is in contrast to a traditional cell that requires an extra select transistor and is not area economic when compared to the new design cell. In this design, the cell adopts poly-poly Fowler-Nordheim tunneling to erase, and an inhibited source voltage is used for the unselected cell to achieve bit erase. It has demonstrated excellent program and erase disturb margins and passed 300 k program/erase (P/E) cycling test. It was found that after P/E cycling stress, the cell gains a better erase disturb immunity.
Keywords :
EPROM; integrated circuit layout; thyristors; tunnelling; P/E cycling stress; SCR design; bit erase; disturb margins; erase disturb immunity; extra select transistor; full-featured EEPROM; high source-coupling ratio design; inhibited source voltage; one-transistor split-gate cells; poly-poly Fowler-Nordheim tunneling; program/erase cycling test; silicon controlled rectifier; Circuit testing; EPROM; Electrons; Flash memory; Silicon compounds; Split gate flash memory cells; Stress; Thyristors; Tunneling; Voltage; Disturb; SCR; full-featured EEPROM; source-coupling ratio; split-gate;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2004.830277
