Title :
Scaling of poly-encapsulated LOCOS for 0.35 μm CMOS technology
Author :
Kenkare, P.U. ; Mazure, C. ; Hayden, J.D. ; Pfiester, J.R. ; Ko, Jiweon ; Kirsch, H.C. ; Ajuria, S.A. ; Crabtree, P. ; Vuong, T.
Author_Institution :
Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA
fDate :
1/1/1994 12:00:00 AM
Abstract :
We demonstrate the scaling of Poly-Encapsulated LOCOS (PELOX) for 0.35 μm CMOS technology without detrimental effects on gate oxide and shallow source/drain junction integrity. As-grown bird´s beak punchthrough is shown to fundamentally limit the scalability of LOCOS-based schemes for narrow nitride features. A quantitative comparison of bird´s beak punchthrough is made between LOCOS, Poly-Buffer LOCOS (PBL), and PELOX. The PELOX scalability is emphasized by evaluating the impact of the polysilicon-sealed cavity length for narrow nitride features. We present the realization of a 1 μm active/isolation pitch fully meeting the geometry and off-leakage requirements of 0.35 μm CMOS technologies (VDS⩽5 V). This field-implant-free isolation module avoids unnecessary process complexity by successfully integrating scaled PELOX with the split well-drive-in scheme. A highlight of this new approach is that the NMOSFET characteristics are largely width-independent down to 0.3 μm dimensions
Keywords :
CMOS integrated circuits; insulated gate field effect transistors; integrated circuit technology; nitridation; oxidation; 0.35 mum; CMOS technology; NMOSFET characteristics; PELOX; active/isolation pitch; bird´s beak punchthrough; field-implant-free isolation module; gate oxide; narrow nitride features; off-leakage requirements; poly-encapsulated LOCOS scaling; polysilicon-sealed cavity length; shallow source/drain junction integrity; split well-drive-in scheme; threshold voltage; BiCMOS integrated circuits; CMOS process; CMOS technology; Degradation; Doping; Etching; Implants; Isolation technology; MOSFET circuits; Scalability;
Journal_Title :
Electron Devices, IEEE Transactions on
