Title :
SiGe-channel heterojunction p-MOSFET´s
Author :
Verdonckt-Vandebroek, Sophie ; Crabbé, Emmanuel F. ; Meyerson, Bernard S. ; Harame, David L. ; Restle, Phillip J. ; Stork, Johannes M C ; Johnson, Jeffrey B.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
1/1/1994 12:00:00 AM
Abstract :
The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFET´s) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFET´s. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n+ polysilicon-gate SiGe p-MOSFET´s have acceptable short-channel behavior at 0.20 μm channel lengths and are preferable to p+ polysilicon-gate p-MOSFET´s for 2.5 V operation. Experimental results of n+-gate modulation-doped SiGe p-MOSFET´s illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm2 /V.s at 300 K and 980 cm2/V.s at 82 K are obtained
Keywords :
Ge-Si alloys; carrier mobility; doping profiles; insulated gate field effect transistors; semiconductor device models; semiconductor doping; semiconductor epitaxial layers; 0.2 micron; 2.5 V; 82 to 300 K; Si cap thickness sensitivity; SiGe-Si; SiGe-channel; channel profile; design parameters; field-effect transistors; gate-oxide thickness sensitivity; graded channel; heterojunction p-MOSFETs; hole mobilities; metal-oxide-semiconductor FET; n+ polysilicon-gate; n+-gate modulation-doped device; p-channel; p+ polysilicon-gate; pseudomorphic epitaxial layers; short-channel behavior; threshold voltage adjustment; transistor gate material; two-dimensional numerical modeling; Design optimization; Epitaxial layers; FETs; Germanium silicon alloys; Heterojunctions; MOSFET circuits; Numerical models; Silicon germanium; Threshold voltage; Transistors;
Journal_Title :
Electron Devices, IEEE Transactions on