Title :
A 3.3-V 12-ns 16-Mb CMOS SRAM
Author :
Goto, Hiroyuki ; Ohkubo, Hiroaki ; Kondou, Kenji ; Ohkawa, Masayoshi ; Mitano, H. ; Horiba, Shinichi ; Soeda, Masakazu ; Hayashi, Fumihiko ; Hachiya, Yutaro ; Shimizu, Toshiyuki ; Ando, Manabu ; Matsuda, Zensuke
Author_Institution :
NEC Corp., Kanagawa, Japan
fDate :
11/1/1992 12:00:00 AM
Abstract :
A 16-Mb CMOS SRAM having an access time of 12 ns under a 3.3-V supply has been developed with a 0.4-μm process technology. An address access time of 12 ns has been achieved by an optimized architecture, the use of an automated transistor size optimizer, and a read-bus midlevel preset scheme (RBMIPS). For better yield and efficient testing, an on-chip test circuit with three test modes has been implemented
Keywords :
CMOS integrated circuits; SRAM chips; integrated circuit testing; 0.4 micron; 12 ns; 16 Mbit; 3.3 V; CMOS SRAM; address access time; automated transistor size optimizer; on-chip test circuit; read-bus midlevel preset scheme; CMOS process; CMOS technology; Circuit testing; Decoding; Delay; Helium; Large-scale systems; Random access memory; SPICE; Telecommunication computing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
