Title :
A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture
Author :
Matsumiya, Masato ; Kawashima, Shoichiro ; Sakata, Makoto ; Ookura, Masahiko ; Miyabo, Toru ; Koga, Tom ; Itabashi, Kazuo ; Mizutani, Kazuhiro ; Shimada, Hiroshi ; Suzuki, Noriyuki
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
fDate :
11/1/1992 12:00:00 AM
Abstract :
Circuit techniques for a reduced-voltage-amplitude data bus, fast access 16-Mb CMOS SRAM are described. An interdigitated bit-line architecture reduces data bus line length, thus minimizing bus capacitance. A hierarchical sense amplifier consists of 32 local sense amplifiers and a current sense amplifier. The current sense amplifier is used to reduce the data bus voltage amplitude and the sensing of the 16-b data bus signals in parallel. Access time of 15 ns and an active power of 165 mW were achieved in a 16-Mb CMOS SRAM. A split-word-line layout memory cell with double-gate pMOS thin-film transistors (TFTs) keeps the transistor width stable while providing high-stability memory cell characteristics. The double-gate pMOS TFT also increases cell-storage node capacitance and soft-error immunity
Keywords :
CMOS integrated circuits; SRAM chips; thin film transistors; 15 ns; 16 Mbit; 165 mW; CMOS SRAM; TFTs; cell-storage node capacitance; current sense amplifier; double-gate pMOS TFT; hierarchical sense amplifier; interdigitated bit-line architecture; local sense amplifiers; memory cell; reduced-voltage-amplitude data bus; soft-error immunity; split-word-line layout; thin-film transistors; Capacitance; Computer architecture; Decoding; MOSFET circuits; Microprocessors; Power dissipation; Random access memory; Thin film transistors; Voltage; Workstations;
Journal_Title :
Solid-State Circuits, IEEE Journal of
