Title :
A cache-based method for accelerating switch-level simulation
Author :
Jones, Larry G. ; Blaauw, David T.
Author_Institution :
Semicond. Syst. Design Technol., Motorola Inc., Austin, TX, USA
fDate :
2/1/1994 12:00:00 AM
Abstract :
Switch-level simulation has become a common means of validating the behavior of MOS circuits. In this paper, we present a new cache-based simulation method that significantly reduces the cost of subnetwork evaluation during switch-level simulation. The method speeds up simulation by as much as a factor of two. While caching may require additional memory, the structural hierarchy can be exploited to quickly identify subnetworks computing identical functions, merge their cache tables, and significantly reduce the memory requirements
Keywords :
MOS integrated circuits; circuit analysis computing; digital simulation; dynamic programming; IC design; MOS circuits; cache table merging; cache-based simulation; function caching; memory requirement reduction; structural hierarchy; subnetwork evaluation; switch-level simulation; Acceleration; Circuit simulation; Circuit testing; Computational modeling; Costs; Databases; Logic design; Logic devices; Space technology; Switching circuits;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
