• DocumentCode
    1019266
  • Title

    A 1-V TFT-load SRAM using a two-step word-voltage method

  • Author

    Ishibashi, Koji ; Takasugi, K. ; Hashimoto, Toshikazu ; Sasaki, Kazuhiko

  • Author_Institution
    Hitachi Ltd., Tokyo
  • Volume
    27
  • Issue
    11
  • fYear
    1992
  • fDate
    11/1/1992 12:00:00 AM
  • Firstpage
    1519
  • Lastpage
    1524
  • Abstract
    A 1-V SRAM using a TFT load cell was developed. Key circuits for obtaining the low-voltage operation are a two-step word-voltage (TSW) method, a submicroampere boosted-level generator using a multivibrator, and a sense amplifier using low-threshold MOSFETs. An access time of 250 ns and a standby current of 0.23 μA were achieved for a 4-kb test chip using a 10.2-μm2 TFT-load cell. This technology is applicable for high-density and single-battery operational SRAMS
  • Keywords
    MOS integrated circuits; SRAM chips; thin film transistors; 1 V; 250 ns; 4 kbit; SRAM; TFT load cell; access time; low-threshold MOSFETs; low-voltage operation; multivibrator; sense amplifier; standby current; static RAM; submicroampere boosted-level generator; two-step word-voltage method; Batteries; CMOS technology; Circuit testing; Electronic equipment; Low voltage; MOSFET circuits; Operational amplifiers; Random access memory; Thin film transistors; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.165331
  • Filename
    165331
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1019266