Title :
A 100-MHz 4-Mb cache DRAM with fast copy-back scheme
Author :
Dosaka, Katsumi ; Konishi, Yasuhiro ; Hayano, Kouji ; Himukashi, Katsumitsu ; Yamazaki, Akira ; Iwamoto, Hisashi ; Kumanoya, Masaki ; Hamano, Hisanori ; Yoshihara, Tsutomu
Author_Institution :
Mitsubishi Electric Corp., Itami, Japan
fDate :
11/1/1992 12:00:00 AM
Abstract :
A 4-Mb cache dynamic random access memory (CDRAM), which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM into a monolithic circuit, is described. This CDRAM has a 100-MHz operating cache, newly proposed fast copy-back (FCB) scheme that realizes a three times faster miss access time over with the conventional copy-back method, and maximized mapping flexibility. The process technology is a quad-polysilicon double-metal 0.7-μm CMOS process, which is the same as used in a conventional 4-Mb DRAM. The chip size of 82.9 mm2 is only a 7% increase over the conventional 4-Mb DRAM. The simulated system performance indicated better performance than a conventional cache system with eight times the cache capacity
Keywords :
CMOS integrated circuits; DRAM chips; buffer storage; 0.7 micron; 100 MHz; 4 Mbit; CMOS process; SRAM; cache DRAM; double-metal; dynamic RAM; fast copy-back scheme; monolithic circuit; quad-polysilicon; static RAM; CMOS process; CMOS technology; Cache memory; Chip scale packaging; Circuits; Costs; Laboratories; Large scale integration; Random access memory; System performance;
Journal_Title :
Solid-State Circuits, IEEE Journal of
