Title :
A 5-V-only operation 0.6-μm flash EEPROM with row decoder scheme in triple-well structure
Author :
Umezawa, Akira ; Atsumi, Shigeru ; Kuriyama, Masao ; Banba, Hironori ; Imamiya, Ken-ichi ; Naruke, Kiyomi ; Yamada, Seiji ; Obi, Etsushi ; Oshikiri, Masamitsu ; Suzuki, Tomoko ; Tanaka, Sumio
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fDate :
11/1/1992 12:00:00 AM
Abstract :
An experimental 4-Mb flash EEPROM has been developed based on 0.6-μm triple-well CMOS technology in order to establish circuit technology for high-density flash memories. A cell size of 2.0×1.8 μm2 has been achieved by using a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11×6.95 mm2, and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm2 by using the minimal cell size (2.0×10 μm2)
Keywords :
CMOS integrated circuits; EPROM; decoding; integrated memory circuits; 0.6 micron; 4 Mbit; 5 V; 5-V-only operation; CMOS technology; erase operation; flash EEPROM; high-density flash memories; negative-gate-biased; row decoder scheme; self-aligned source; source erase scheme; triple-well structure; CMOS process; CMOS technology; Circuits; Decoding; EPROM; Fabrication; Flash memory; Synthetic aperture sonar; Tunneling; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
