A 9.5-Gb/s Si-bipolar ECL array

Author

Tamamura, Masaya ; Shiotsu, Shinichi ; Hojo, Masayasu ; Nomura, Katsunobu ; Emori, Shinji ; Ichikawa, Hiromichi ; Akai, Takao

Author_Institution

Fujitsu Ltd., Kawasaki, Japan

Volume

27

Issue

11

fYear

1992

fDate

11/1/1992 12:00:00 AM

Firstpage

1575

Lastpage

1578

Abstract

A 9.5-Gb/s Si-bipolar ECL array that has a gate delay of 35 ps, a risetime of 45 ps, and a falltime of 40 ps is described. The ECL circuit design and the chip layout were optimized. A Si-bipolar process with 0.3-μm emitter width and packaging capable of accepting 10-GHz signal were used. The array was used in three key circuits of an optical communication system: a decision circuit, a 4:1 multiplexer, and a 1:4 demultiplexer. Operation of the decision circuit at 9.5 Gb/s, of the 4:1 multiplexer at 6.7 Gb/s, and of the 1:4 demultiplexer at 6.7 Gb/s were confirmed

Keywords

bipolar integrated circuits; demultiplexing equipment; elemental semiconductors; emitter-coupled logic; logic arrays; multiplexing equipment; optical communication equipment; silicon; 0.3 micron; 10 GHz; 35 ps; 45 ps; 6.7 Gbit/s; 9.5 Gbit/s; ECL array; ECL circuit design; Si bipolar logic circuit; chip layout; decision circuit; demultiplexer; falltime; gate delay; multiplexer; optical communication system; packaging; risetime; Circuit synthesis; Delay effects; Design optimization; Multiplexing; Optical arrays; Optical fiber communication; Packaging; Reflection; Resistors; Signal processing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.165338

Filename

165338