• DocumentCode
    1020173
  • Title

    Topology dependence of floating gate faults in MOS integrated circuits

  • Author

    Renovell, M. ; Cambon, G.

  • Author_Institution
    Université des Sciences et Techniques du Languedoc, Laboratoire d´Automatique et de Microélectronique de Montpellier, Laboratoire associé au CNRS (UA 371), Montpellier, France
  • Volume
    22
  • Issue
    3
  • fYear
    1986
  • Firstpage
    152
  • Lastpage
    153
  • Abstract
    Models for floating gate faults in MOS integrated circuits are introduced. It is experimentally demonstrated that these models are mask-topology-dependent. The logic state of the gate can be stuck-at, undefined or influenced. In the case of an influenced gate a `pseudo-MOS transistor¿ is defined.
  • Keywords
    CMOS integrated circuits; failure analysis; integrated circuit testing; masks; CMOS technology; MOS integrated circuits; circuit testing; domino structure; floating gate faults; influenced gate; logic-state; mask topology; pseudoMOS transistor;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19860106
  • Filename
    4256292
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1020173