• DocumentCode
    1020370
  • Title

    Floating substrate effects on speed performance in scaled CMOS/SOS circuits

  • Author

    Hatano, Hiroshi

  • Author_Institution
    Toshiba Corporation, Semiconductor Device Engineering Laboratory, Research & Development Center, Kawasaki, Japan
  • Volume
    22
  • Issue
    4
  • fYear
    1986
  • Firstpage
    177
  • Lastpage
    179
  • Abstract
    Floating substrate effects on speed degradation in 2 ¿m SOS circuits have been investigated. It has been found that the drain-substrate capacitive coupling is dominant in highly doped substrate devices, based on experimental results obtained from CMOS ring oscillators. Cycle-time-dependent sense amplifier output transition times have also been explained by this capacitive coupling.
  • Keywords
    CMOS integrated circuits; VLSI; 2 micron design rules; VLSI; cycle-time dependence; doped substrate devices; drain-substrate capacitive coupling; floating substrate effects; monolithic IC; output transition times; scaled CMOS/SOS circuits; sense amplifier; speed performance;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19860124
  • Filename
    4256311
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1020370