Title :
Floating substrate effects on speed performance in scaled CMOS/SOS circuits
Author_Institution :
Toshiba Corporation, Semiconductor Device Engineering Laboratory, Research & Development Center, Kawasaki, Japan
Abstract :
Floating substrate effects on speed degradation in 2 ¿m SOS circuits have been investigated. It has been found that the drain-substrate capacitive coupling is dominant in highly doped substrate devices, based on experimental results obtained from CMOS ring oscillators. Cycle-time-dependent sense amplifier output transition times have also been explained by this capacitive coupling.
Keywords :
CMOS integrated circuits; VLSI; 2 micron design rules; VLSI; cycle-time dependence; doped substrate devices; drain-substrate capacitive coupling; floating substrate effects; monolithic IC; output transition times; scaled CMOS/SOS circuits; sense amplifier; speed performance;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19860124
