A VLSI sequencer chip for ATM traffic shaper and queue manager

The authors propose to control user traffic at two places in an asynchronous transfer model (ATM) network: at the user-network interface (UNI) by a traffic enforcer, and at the network-node interface (NNI) by a queue manager. The traffic enforcer adopted in this work contains a buffer to delay and reshape the violating cells that do not comply with some agreed-upon traffic parameters, and thus is also called a traffic shaper. The queue manager manages the queued cells in network nodes in such a way that higher priority cells are always served first, low-priority cells are discarded when the queue is full, and any interference between same-priority cells is prevented. Architectures for the traffic shaper and the queue manager are proposed. A key component, called the sequencer chip, has been implemented and tested to realize both architectures. The sequencer chip uses 1.2-μm CMOS technology. It contains about 150 K transistors, has a die size of 7.5 mm×8.3 mm, and is packages in a 223-pin ceramic pin-grid-array (PGA) carrier