Title :
Performance analysis of interconnection networks of a modified model for synchronous multiprocessors
Author :
Pombortsis, Andrew S. ; Halatsis, Constantin
Author_Institution :
University of Thessaloniki, Digital Systems & Computers Laboratory, Department of Physics & Mathematics, Thessaloniki, Greece
Abstract :
The letter presents an analysis of a modified model for synchronous multiprocessor systems. In this model, besides the shared memory modules, each processor has a private memory. The memory references of each processor are not uniformly distributed among the memory modules. The interconnection network is considered to be either a crossbar or a shared bus.
Keywords :
computer architecture; multiprocessing systems; performance evaluation; switching networks; computer architecture; crossbar bus; interconnection networks; modified model; performance analysis; private memory; shared bus; shared memory modules; switching network; synchronous multiprocessors;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19860155
