Title :
Test set compaction for combinational circuits
Author :
Chang, Jau-Shien ; Lin, Chen-Shang
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
11/1/1995 12:00:00 AM
Abstract :
Test set compaction for combinational circuits is studied in this paper. Two active compaction methods based on essential faults are developed to reduce a given test set. The special feature is that the given test set will be adaptively renewed to increase the chance of compaction. In the first method, forced pair-merging, pairs of patterns are merged by modifying their incompatible specified bits without sacrificing the original fault coverage. The other method, essential fault pruning, achieves further compaction from removal of a pattern by modifying other patterns of the test set to detect the essential faults of the target pattern. With these two developed methods, the compacted test size on the ISCAS´85 benchmark circuits is smaller than that of COMPACTEST by more than 20%, and 12% smaller than that by ROTCO+COMPACTEST
Keywords :
automatic testing; combinational circuits; integrated circuit testing; logic testing; ISCAS´85 benchmark circuits; active compaction methods; combinational circuits; essential fault pruning; essential faults; forced pair-merging; incompatible specified bits; test set compaction; Benchmark testing; Buffer storage; Circuit faults; Circuit testing; Combinational circuits; Compaction; Electrical fault detection; Fault detection; Integrated circuit testing; Test pattern generators;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
