• DocumentCode
    1021115
  • Title

    New hardware scheme supporting precise exception handling for out-of-order execution

  • Author

    Hwang, G.C. ; Kyung, C.M.

  • Author_Institution
    Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
  • Volume
    30
  • Issue
    1
  • fYear
    1994
  • fDate
    1/6/1994 12:00:00 AM
  • Firstpage
    16
  • Lastpage
    17
  • Abstract
    A new hardware scheme is proposed to resolve data and control hazards and assure precise exception on out-of-order execution in a microarchitecture with multiple pipelined functional units. The core of the proposed hardware is a register file called CARF, which is made of CAM (content-addressable memory), with an efficient state-transition mechanism for precise exception handling and prompt branch misprediction recovery
  • Keywords
    content-addressable storage; exception handling; parallel architectures; pipeline processing; CAM; CARF; branch misprediction recovery; content-addressable memory; data/control hazards; hardware scheme; microarchitecture; multiple pipelined functional units; out-of-order execution; precise exception handling; register file; state-transition mechanism;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19940022
  • Filename
    260572
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1021115