On squashing hierarchical designs [VLSI]

The problem of partially expanding a hierarchical VLSI design is examined, with the goal of reducing the number of levels of hierarchy while incurring minimal design-size expansion. While the general problem appears NP-hard, an important special case is considered, where the number of levels of hierarchy is reduced by one. For this special case, an exact algorithm is developed, based on network-flow techniques. Using this algorithm, a heuristic for the general problem is then developed and experimentally evaluated on a collection of VLSI designs