• DocumentCode
    1022343
  • Title

    Generation of simple limit cycles in digital circuits

  • Author

    Tan, E.C.

  • Author_Institution
    Royal Melbourne Institute of Technology, Department of Communication & Electronic Engineering, Melbourne, Australia
  • Volume
    22
  • Issue
    9
  • fYear
    1986
  • Firstpage
    459
  • Lastpage
    560
  • Abstract
    Readily predictable elementary limit cycles can be generated using a first-order digital circuit subject to magnitude truncation that is excited by constant inputs. Conditions for sustaining specific length and magnitude of limit cycles are given. The results will be useful for educational demonstrations and for hardware testing of certain digital circuits.
  • Keywords
    digital circuits; limit cycles; constant inputs; educational demonstrations; first-order digital circuit; hardware testing of certain digital circuits; limit cycles generation; magnitude truncation; predictable elementary limit cycles; simple limit cycles in digital circuits;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19860312
  • Filename
    4256506
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1022343