Title :
Generation of simple limit cycles in digital circuits
Author_Institution :
Royal Melbourne Institute of Technology, Department of Communication & Electronic Engineering, Melbourne, Australia
Abstract :
Readily predictable elementary limit cycles can be generated using a first-order digital circuit subject to magnitude truncation that is excited by constant inputs. Conditions for sustaining specific length and magnitude of limit cycles are given. The results will be useful for educational demonstrations and for hardware testing of certain digital circuits.
Keywords :
digital circuits; limit cycles; constant inputs; educational demonstrations; first-order digital circuit; hardware testing of certain digital circuits; limit cycles generation; magnitude truncation; predictable elementary limit cycles; simple limit cycles in digital circuits;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19860312
