A content addressable memory circuit using Josephson junctions

This paper describes a content addressable memory circuit using Josephson NDRO memory cells, in which a novel Josephson multi-response resolver is included. The memory circuit proposed here performs the searching functions such as coincidence, incoincidence and don´t-care function, in addition to the conventional memory function of writing and reading. In order to investigate how a high performance operation can be achieved, computer simulations have been made. Simulation results show that the cycle time of memory operation is 60psec, power dissipation is 0.28μW/cell and the cycle time of multi-response resolver operation is 153psec.