Author :
Malhi, S.D.S. ; Bean, K.E. ; Sunderesan, R. ; Hite, L.R.
Author_Institution :
Texas Instruments Incorporated, Semiconductor Process & Design Center, Dallas, USA
Abstract :
A CMOS structure where the source and drain terminals of the MOSFETs are in polysilicon overlaid on top of a thick oxide and the channel is in single-crystal silicon is described, utilising a 970°C SiH4 CVD process which simultaneously deposits epitaxial silicon on the exposed silicon substrate and polysilicon on oxide. The structure allows a more compact CMOS inverter layout and reduced source/drain parasitic capacitances.
Keywords :
CMOS integrated circuits; chemical vapour deposition; integrated circuit technology; integrated logic circuits; invertors; vapour phase epitaxial growth; 970°C SiH4 CVD process; CMOS structure; VPE; compact CMOS inverter layout; packing density; polysilicon; reduced source/drain parasitic capacitances; simultaneous epitaxial Si and poly-Si deposition; single crystal Si channel; thick oxide;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19860406
