Power-Substrate Static Thermal Characterization Based on a Test Chip

Thermal simulation is, nowadays, a basic tool to predict temperature distributions and heat fluxes of complex packages and modules. These variables are of main importance in high-power assemblies to analyze and predict their reliability limits. Nevertheless, the simulation results can be inaccurate due to the uncertainty of the values of the physical parameters involved in the models, as it is the case for the thermal conductivity of the dielectric layers (ceramics and composites) of the main families of power substrates [direct copper bonded (DCB) and insulated metal substrate (IMS)]. We propose a methodology for the in situ determination of these thermal conductivities under true operation conditions. Three test assemblies based on a thermal test chip and different types of power substrates (two IMS and one DCB) have been characterized in order to deduce their thermal resistance. Three-dimensional numerical models of the assemblies have also been developed. Thereby, the thermal conductivity of the critical layers is derived by minimizing the error between the experimental and the simulated thermal resistances. From the subsequent simulation results, the vertical temperature distributions are analyzed in order to predict the thermal stresses of the different layers inside the substrates.