Josephson data latch for frequency agile shift registers

A Josephson data latch was designed and simulated with the SPICE program. The data latches were connected in series to form a shift register which showed frequency agile operation. The novel latches were based on Direct Coupled Logic OR gates to obtain high speed performance. Latches were triggered by the rising edge of the clock voltage to provide a sampling interval. Switching of the triggering junction to the resistive state deactivated the latch´s input response which prevented racing of the two phase logic. Simulations showed proper operation of the shift register at frequencies up to 15 GHz. The wide operating margins of the circuit are suited to LSI fabrication. Comparison of the model junction to currently available Josephson technology indicated that real chips should be capable of frequency agile operation in the multigigahertz range.