Title :
Electrostatic discharge testing of integrated circuits using step-stress transients or multiple transients
Author :
Shaw, R.N. ; Enoch, R.D.
Author_Institution :
British Telecom Research Laboratories, Ipswich, UK
Abstract :
A model has been developed which accounts for the damage behaviour of the on-chip input protection diode of an IC subjected either to multiple-transient testing or to step-stress testing.
Keywords :
discharges (electric); integrated circuit testing; overvoltage protection; ESD testing; IC; damage behaviour; electrostatic discharge testing; integrated circuits; model; multiple transients; multiple-transient testing; on-chip input protection diode; step-stress testing; step-stress transients;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19860558
