A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM

Author

Terada, Yasushi ; Kobayashi, Kazuo ; Nakayama, Takeshi ; Arima, Hideaki ; Yoshihara, Tsutomu

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

Volume

23

Issue

1

fYear

1988

Firstpage

86

Lastpage

90

Abstract

An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs.<>

Keywords

CMOS integrated circuits; PROM; integrated memory circuits; random-access storage; DRAM sense amplifier; EEPROM; FLOTOX-type; NVRAM; back-up DRAM; data latch; dynamic RAM cell; high-density applications; memory cell; n-well CMOS process; nonvolatile RAM; Capacitors; DRAM chips; EPROM; Equivalent circuits; Latches; Nonvolatile memory; Pulsed power supplies; Random access memory; Read-write memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.261

Filename

261