Title :
Synergistic fault-tolerance for memory chips
Author :
Stapper, Charles H. ; Lee, Hsing-San
Author_Institution :
IBM, Essex Junction, VT, USA
fDate :
9/1/1992 12:00:00 AM
Abstract :
The discovery of a principle of synergistic fault tolerance is described, and it is shown analytically why it occurs. The performance of its hardware implementation, in the form of a VLSI memory chip, is reported. An analysis of the error-correction scheme implemented in the hardware is presented, and limitations to the use of error-correcting codes for fault tolerance are explained. Methods for circumventing these limitations with the use of redundant circuits are discussed, analyzing the effect of bitline and wordline redundancy. The result of the analysis shows how the combination of error-correcting codes with redundant circuitry results in a fault-tolerance synergism
Keywords :
DRAM chips; VLSI; error correction codes; fault tolerant computing; VLSI memory chip; bitline redundancy; error-correcting codes; error-correction; fault-tolerance synergism; memory chips; redundant circuits; synergistic fault tolerance; wordline redundancy; Circuit faults; Error correction codes; Fabrication; Fault tolerance; Hardware; Integrated circuit yield; Manufacturing; Mathematical analysis; Protection; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
