A monolithic 480 Mb/s parallel AGG/decision/clock-recovery circuit in 1.2-μm CMOS

Author

Hu, Timothy H. ; Gray, Paul R.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

28

Issue

12

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

1314

Lastpage

1320

Abstract

A parallel architecture for high-data-rate AGC/decision/clock-recovery circuit, recovering digital NRZ data in optical-fiber receivers, is described. Improvement over traditional architecture in throughput is achieved through the use of parallel signal paths. An experimental prototype, fabricated in a 1.2-μm double-poly double-metal n-well CMOS process, achieves a maximum bit rate of 480 Mb/s. The chip contains variable gain amplifiers, clock recovery, and demultiplexing circuits. It yields a BER of 10^-11 with an 18 mV_p-p differential input signal. The power consumption is 900 mW from a single 5 V supply

Keywords

CMOS integrated circuits; automatic gain control; data communication equipment; demultiplexing equipment; digital communication systems; mixed analogue-digital integrated circuits; optical receivers; 1.2 micron; 480 Mbit/s; 5 V; 900 mW; BER; bit error rate; clock-recovery circuit; decision circuit; demultiplexing circuits; digital NRZ data; double-poly double-metal process; high-data-rate; n-well CMOS process; optical-fiber receivers; parallel AGG; parallel architecture; single 5 V supply; variable gain amplifiers; Bit rate; CMOS process; Circuits; Clocks; Optical receivers; Optical signal processing; Parallel architectures; Prototypes; Stimulated emission; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.262005

Filename

262005