VIPER: a VLIW integer microprocessor

Author

Gray, Jeffrey ; Naylor, Andrew ; Abnous, Arthur ; Bagherzadeh, Nader

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA

Volume

28

Issue

12

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

1377

Lastpage

1382

Abstract

This paper describes the design and implementation of a very long instruction word (VLTW) microprocessor. The VLIW integer processor (VIPER) contains four pipelined functional units and can achieve 0.25-cycle-per-instruction performance. The processor is capable of performing multiway branch operations, two load/store operations, or up to four ALU operations in each clock cycle, with full register file access to each functional unit. Designed in twelve months, the processor is integrated with an instruction cache controller and a data cache, requiring 450,000 transistors and a die size of 12.9 mm×9.1 mm in a 1.2-μm technology

Keywords

CMOS integrated circuits; VLSI; microprocessor chips; parallel architectures; pipeline processing; 1.2 micron; ALU operations; VIPER; VLIW integer microprocessor; data cache; full register file access; instruction cache controller; load/store operations; multiway branch operations; pipelined functional units; very long instruction word; Clocks; Computer architecture; Hardware; Microprocessors; Parallel processing; Processor scheduling; Reduced instruction set computing; Registers; VLIW; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.262015

Filename

262015