Title :
Analysis of latchup and parasitic effects in merged BiCMOS structures
Author :
Rofail, Samir S. ; Elmasry, Mohamed I.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
fDate :
12/1/1993 12:00:00 AM
Abstract :
Latchup and performance degradation due to the parasitic elements in merged BiCMOS structures are studied. Circuit simulations using HSPICE and analytical characterisation are used to describe the parasitic components and model their effects on the output voltage switching characteristics and delay time. A latchup factor is defined to relate the degree of performance degradation to the device and key circuit parameters
Keywords :
BiCMOS integrated circuits; SPICE; circuit analysis computing; electrical faults; equivalent circuits; semiconductor device models; switching; HSPICE; analytical characterisation; circuit simulations; delay time; latchup analysis; latchup factor; merged BiCMOS structures; model; output voltage switching characteristics; parasitic effects; performance degradation; BiCMOS integrated circuits; CMOS process; Circuit simulation; Degradation; Delay effects; Semiconductor device modeling; Silicon; Switching circuits; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
