• DocumentCode
    1027281
  • Title

    VLSI architecture of bit-serial quasicyclic encoders

  • Author

    Wang, Qijie ; El Guibaly, F.H. ; Bhargava, V.K.

  • Author_Institution
    University of Victoria, Department of Electrical Engineering, Victoria, Canada
  • Volume
    22
  • Issue
    22
  • fYear
    1986
  • Firstpage
    1170
  • Lastpage
    1171
  • Abstract
    A bit-serial algorithm for the multiplication of elements in the vector space of finite dimension is presented. Based on the algorithm, a VLSI architecture of quasicyclic (QC) encoders is shown. Compared with that of conventional QC encoders, the proposed architecture is more regular, simpler and programmable. It also offers designers more flexibility for choosing available VLSI techniques. In addition, it can easily be changed to accommodate any QC coding strategies.
  • Keywords
    VLSI; digital integrated circuits; encoding; multiplying circuits; VLSI architecture; bit-serial quasicyclic encoders; digital IC; finite dimension; multiplication; vector space;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19860801
  • Filename
    4257017
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1027281