A memory-based high-speed digital delay line with a large adjustable length

Author

Mattausch, Hans-jürgen ; Matthiesen, Fred ; Härtl, Jutta ; Tielert, Reinhard ; Jacobs, Erwin P.

Author_Institution

Siemens AG, Munich, West Germany

Volume

23

Issue

1

fYear

1988

Firstpage

105

Lastpage

110

Abstract

The digital delay line concept is based on a dynamic three-transistor cell memory, with pointer access and offers high operating frequency, large maximum length, and low power dissipation. The adjustable delay requires only a small overhead for control logic. An experimental chip with 60 K transistors, which utilizes this concept, has been built in a 1.5- mu m CMOS technology. The adjustable delay ranges from 1 to 4096 clock cycles for a 4-bit-wide data word. Correct operation of the chip has been verified for clock frequencies in the range of 3 kHz to 30 MHz. Therefore the circuit is suitable for audio as well as video applications.<>

Keywords

CMOS integrated circuits; VLSI; delay lines; digital integrated circuits; 1.5 micron; 3 kHz to 30 MHz; 4 bit; CMOS technology; VLSI; adjustable delay; adjustable length; audio applications; clock frequencies; control logic; digital delay line; dynamic three-transistor cell memory; high operating frequency; high-speed; large maximum length; low power dissipation; monolithic IC; pointer access; video applications; CMOS logic circuits; CMOS technology; Clocks; Delay lines; Frequency; Jacobian matrices; Manufacturing automation; Office automation; Power dissipation; Streaming media;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.265

Filename

265