Effect of surface fields on the breakdown voltage of planar silicon p-n junctions

The effect of surface fields on the breakdown voltage of planar silicon diodes is studied experimentally and theoretically. It is shown that the breakdown voltage can be modulated over a very wide range by the application of an external surface field and that it tends to saturation at a maximum and at a minimum value as the gate voltage is varied in such a way as to deplete the lowly doped and highly doped sides of the junction, respectively. Both the high- and the low-voltage saturation of the breakdown voltage appear to be due to the formation of field-induced junctions which prevent further variation in the shape of the depletion region, and hence the breakdown voltage. Between these two extremes, the breakdown voltage is found to be approximately given by +constant, where VGis the gate-to-substrate potential. The slope approaches unity for low substrate impurity concentrations and for small oxide thicknesses. Numerical solutions of the two-dimensional potential distribution problem give results which are in general agreement with the above experimental observations.