DocumentCode :
1028090
Title :
Hardware Implementation for a Genetic Algorithm
Author :
Chen, Pei-Yin ; Chen, Ren-Der ; Chang, Yu-Pin ; Shieh, Leang-San ; Malki, Heidar A.
Author_Institution :
Nat. Cheng Kung Univ., Tainan
Volume :
57
Issue :
4
fYear :
2008
fDate :
4/1/2008 12:00:00 AM
Firstpage :
699
Lastpage :
705
Abstract :
A genetic algorithm (GA) can find an optimal solution in many complex problems. GAs have been widely used in many applications. A flexible-very-large-scale integration intellectual property for the GA has been proposed in this paper. This algorithm can dynamically perform various population sizes, fitness lengths, individual lengths, fitness functions, crossover operations, and mutation-rate settings to meet the real-time requirements of various GA applications. It can be seen from the simulation results that our design works very well for the three examples running at an 83-MHz clock frequency.
Keywords :
VLSI; genetic algorithms; industrial property; integrated circuit design; GA; genetic algorithm; hardware implementation; very-large-scale integration intellectual property; Field-programmable gate array (FPGA); Verilog; genetic algorithm (GA); intellectual property (IP); software system;
fLanguage :
English
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9456
Type :
jour
DOI :
10.1109/TIM.2007.913807
Filename :
4425258
Link To Document :
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