Title :
Novel sorter architecture for image processing rank order filters
Author_Institution :
Siemens AG, ZT ZFE ME 22, Mÿnchen, West Germany
Abstract :
In this letter a novel sorter architecture for two-dimensional rank order filters is presented. Rank order filters are widely used in image processing applications to smooth noisy images without perturbing edge structures. The main element of such filters is a sorter. In the letter a parallel sorting network is described, based on Batcher´s odd-even merge algorithm. The required chip area of the sorter network is proportional to N(log2N)[(log2 N) + 1], where N is the number of pixels to be sorted. An example of a 25-pixel sorter network is given.
Keywords :
VLSI; computer architecture; computerised picture processing; digital integrated circuits; parallel processing; sorting; two-dimensional digital filters; 25 pixel; 25-pixel sorter network; Batcher´s odd-even merge algorithm; chip area; image processing rank order filters; parallel sorting network; smooth noisy images; sorter architecture; sorter network; two dimensional digital filters; two-dimensional rank order filters;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19870033