A new dynamic test vector compaction for automatic test pattern generation

Author

Ayari, Bechir ; Kaminska, Bozena

Author_Institution

Ecole Polytech., Montreal, Que., Canada

Volume

13

Issue

3

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

353

Lastpage

358

Abstract

A new approach for dynamic test vector compaction, for combinational logic circuits, called COMPACT, is proposed. A new data structure of test vectors permits easy verification of compactability between test vectors with minimal memory requirements. Experimental results obtained by adding the proposed algorithm to a simple PODEM program and applying it to the ISCAS-85 benchmark circuits are presented. The resulting test vector reduction is up to 40% for small circuits and around 50% for the large circuits (over 1000 gates)

Keywords

automatic testing; combinatorial circuits; integrated circuit testing; logic testing; COMPACT; ISCAS-85 benchmark circuits; PODEM program; automatic test pattern generation; combinational logic circuits; compactability; data structure; dynamic test vector compaction; minimal memory requirements; test vector reduction; Automatic test pattern generation; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Compaction; Data structures; Fault detection; Logic testing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.265676

Filename

265676