An approach to the analysis and detection of crosstalk faults in digital VLSI circuits

Author

Rubio, Antonio ; Itazaki, Noriyoshi ; Xu, Xiaole ; Kinoshita, Kozo

Author_Institution

Dept. of Phys., Balearic Islands Univ., Palma, Spain

Volume

13

Issue

3

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

387

Lastpage

395

Abstract

The continuous reduction of the device size in integrated circuits and the increase in the switching rate cause parasitic capacitances between conducting layers to become dominant and cause logic errors in the circuits. Therefore, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this class of faults. This paper presents a logic level characterization and fault model for crosstalk faults. The authors also show how a fault list of such faults can be generated from the layout data, and give an automatic test pattern generation procedure for them

Keywords

VLSI; automatic testing; crosstalk; fault location; integrated circuit testing; integrated logic circuits; logic testing; automatic test pattern generation procedure; capacitive couplings; conducting layers; crosstalk faults; device size; digital VLSI circuits; fault list; fault model; logic errors; logic faults; logic level characterization; parasitic capacitances; switching rate; Automatic test pattern generation; Circuit faults; Coupling circuits; Crosstalk; Electrical fault detection; Fault detection; Logic circuits; Logic devices; Parasitic capacitance; Switching circuits;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.265680

Filename

265680