DocumentCode
1030143
Title
Optimization of the Scheduler for the Non-Blocking High-Capacity Router
Author
Petrovic, Milos ; Smiljanic, Aleksandra
Author_Institution
Belgrade Univ., Belgrade
Volume
11
Issue
6
fYear
2007
fDate
6/1/2007 12:00:00 AM
Firstpage
534
Lastpage
536
Abstract
The sequential greedy scheduling (SGS) is a scalable maximal matching algorithm that provides non-blocking in an Internet router with input buffers and a cross-bar. In this paper, we will present the FPGA design of the SGS scheduler. We have optimized scheduler components, and we will prove their correct functioning. The scheduler optimization significantly reduces the worst-case packet delay through the router.
Keywords
Internet; delays; field programmable gate arrays; scheduling; telecommunication network routing; FPGA design; Internet router; cross-bar; input buffers; maximal matching algorithm; nonblocking high-capacity router; scheduler optimization; sequential greedy scheduling; worst-case packet delay; Algorithm design and analysis; Circuit testing; Delay; Fabrics; Field programmable gate arrays; Packet switching; Performance analysis; Processor scheduling; Scalability; Scheduling algorithm;
fLanguage
English
Journal_Title
Communications Letters, IEEE
Publisher
ieee
ISSN
1089-7798
Type
jour
DOI
10.1109/LCOMM.2007.061653
Filename
4257456
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