Title :
Optimization of the Scheduler for the Non-Blocking High-Capacity Router
Author :
Petrovic, Milos ; Smiljanic, Aleksandra
Author_Institution :
Belgrade Univ., Belgrade
fDate :
6/1/2007 12:00:00 AM
Abstract :
The sequential greedy scheduling (SGS) is a scalable maximal matching algorithm that provides non-blocking in an Internet router with input buffers and a cross-bar. In this paper, we will present the FPGA design of the SGS scheduler. We have optimized scheduler components, and we will prove their correct functioning. The scheduler optimization significantly reduces the worst-case packet delay through the router.
Keywords :
Internet; delays; field programmable gate arrays; scheduling; telecommunication network routing; FPGA design; Internet router; cross-bar; input buffers; maximal matching algorithm; nonblocking high-capacity router; scheduler optimization; sequential greedy scheduling; worst-case packet delay; Algorithm design and analysis; Circuit testing; Delay; Fabrics; Field programmable gate arrays; Packet switching; Performance analysis; Processor scheduling; Scalability; Scheduling algorithm;
Journal_Title :
Communications Letters, IEEE
DOI :
10.1109/LCOMM.2007.061653
