Title :
A new multistandard video processor including deflection drive circuits which is controlled by digital process
Author :
Baba, Y. ; Yamazaki, N. ; Sengoku, Y. ; Nishiyama, S. ; Shimizu, H.
Author_Institution :
Sony Corp., Tokyo, Japan
fDate :
8/1/1989 12:00:00 AM
Abstract :
The authors describe a novel multistandard video processor which uses the counted-down method in the synchronization block. The processor consists of luminance, chrominance and deflection signal processing blocks. The count-down method is used in both the horizontal and the vertical synchronization circuits of the deflection signal processing block. Because a 50/60 identification circuit is installed and the chrominance signal processing block can receive PAL (phase alteration line) and NTSC (National Television System Committee) signals using this video processor and a SECAM (sequential and memory) decoder, it is possible to construct a multistandard system TV receiver. Systematic development work has been done to maximize the performance of the functional blocks and to minimize the number of pins and external components
Keywords :
colour television receivers; picture processing; television standards; video signals; NTSC; National Television System Committee; PAL; SECAM; chrominance; counted-down method; decoder; deflection drive circuits; deflection signal; digital process controlled; horizontal synchronisation circuit; identification circuit; luminance; multistandard system TV receiver; multistandard video processor; phase alteration line; sequential and memory; synchronization block; vertical synchronization circuits; Circuits; Digital control; Frequency synchronization; Ignition; Jitter; Noise level; Pins; Process control; Video signal processing; White noise;
Journal_Title :
Consumer Electronics, IEEE Transactions on
