A DSP line equalizer VLSI for TCM digital subscriber-line transmission

The architecture of a line equalizer using digital-signal-processing (DSP) techniques is described. The equalizer is utilized in 320-kb/s time-compression multiplexing (TCM) subscriber-line transmission systems in the integrated services digital network (ISDN). It consists of two digital filter blocks, called the square root f equalizer and the bridged-tap equalizer, and gain- and timing-control blocks. The square root f equalizer achieves the processing speed of 20 MOPS by a powerful arithmetic unit composed of multipliers and adders. It provides an FIR filter with nine taps which satisfies an accurate equalization for the 1.92-Msample/s data. The bridged-tap equalizer performs both the adaptation algorithm of the square root f equalizer and the decision-feedback algorithm. The microprogram control enables the hardware to be shared between these functions and assures flexibility. Algorithm-oriented instructions implemented in the ALU realize high-speed execution of the decision-feedback algorithm with a simple architecture. The 11.3-mm*8.5-mm chip with 61 K transistors has been implemented using 1.5- mu m double-metal-layer CMOS technology.<>