Low temperature InP/Si technology: from Si substrate preparation to epitaxial growth

Author

Gonzalez, L. ; Gonzalez, Y. ; Dotor, M.L. ; Golmayo, D. ; Gomez, David ; Briones, F.

Author_Institution

Centro Nacional de Microelectronica, CSIC, Madrid

Volume

30

Issue

3

fYear

1994

fDate

2/3/1994 12:00:00 AM

Firstpage

269

Lastpage

271

Abstract

InP layers have been grown on Si(001) substrates by using a low temperature process, both for the Si surface preparation (400°C<T _Si<550°C) and for the growth process itself (T_g<350°C) using solid source atomic layer molecular beam epitaxy. Strain-free InP on Si layers, with an etch pit density of ~1-2×10⁷ cm^-2, showing an excellent morphology and good optical quality have been obtained using a buffer layer involving strain layer superlattices (SLS) of elastically dissimilar materials. This result implies an actual advancement towards monolithic integration of III-V devices to conventional CMOS-Si circuits

Keywords

III-V semiconductors; indium compounds; molecular beam epitaxial growth; semiconductor technology; silicon; substrates; 350 C; 400 to 550 C; CMOS; III-V devices; InP layers; InP-Si; InP/Si technology; Si; Si substrate preparation; Si(001) substrates; buffer layer; elastically dissimilar materials; epitaxial growth; etch pit density; low temperature process; monolithic integration; morphology; optical quality; strain layer superlattices;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:19940124

Filename

267197