DocumentCode
1032158
Title
An Area-Efficient FFT Architecture for OFDM Digital Video Broadcasting
Author
Jiang, Richard M.
Author_Institution
Peking Univ., Beijing
Volume
53
Issue
4
fYear
2007
Firstpage
1322
Lastpage
1326
Abstract
In this paper, a novel high-performance 8k-point fast Fourier transform (DFT) processor architecture for OFDM digital video broadcasting(DVB) is proposed based on a novel radix-8 FFT architecture. Distributed arithmetic (DA) is used to implement the basic 8-point FFTs directly, where the hardware cost of complex multipliers and adders can be greatly reduced. The twiddle multiplications are performed by CORDIC-based twiddle multipliers. The results show that the proposed processor architecture can greatly save the area cost while keeping a high-speed processing speed, which may be attractive for many real-time DVB-T systems.
Keywords
OFDM modulation; digital video broadcasting; distributed arithmetic; fast Fourier transforms; microprocessor chips; television receivers; CORDIC-based twiddle multipliers; OFDM digital video broadcasting; area-efficient FFT architecture; distributed arithmetic; high-performance radix-8 point fast Fourier transform; high-speed processing speed; processor architecture; twiddle multiplications; Adders; Arithmetic; Costs; Digital video broadcasting; Discrete Fourier transforms; Fast Fourier transforms; Flexible printed circuits; Hardware; OFDM; Real time systems;
fLanguage
English
Journal_Title
Consumer Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0098-3063
Type
jour
DOI
10.1109/TCE.2007.4429219
Filename
4429219
Link To Document