DocumentCode :
1032293
Title :
Efficient one-dimensional systolic array realization of the discrete Fourier transform
Author :
Beraldin, J.A. ; Aboulnasr, Tyseer ; Steenaart, Willem
Author_Institution :
Nat. Res. Council Canada, Ottawa, Ont., Canada
Volume :
36
Issue :
1
fYear :
1989
Firstpage :
95
Lastpage :
100
Abstract :
A one-dimensional systolic array realizing the discrete Fourier transform (DFT) of nonstop input sequences is presented. Two arrays having different output schemes, i.e. pipelined and bus-oriented output paths, are introduced. Both arrays require N cells and take N clock cycles to produce a complete N-point DFT. The latency time for the pipeline scheme is twice that of the bus-oriented scheme. For both arrays, a continuous flow of input vectors is allowed and no idle period is required between successive vectors. The array coefficients are static and thus stored-product ROMs (read-only memories) can be used in place of multipliers to limit cost as well as eliminate errors due to coefficient quantization.<>
Keywords :
Fourier transforms; cellular arrays; computerised signal processing; parallel algorithms; parallel architectures; pipeline processing; DFT; bus-oriented scheme; discrete Fourier transform; latency time; nonstop input sequences; one-dimensional systolic array; pipeline scheme; read-only memories; stored-product ROMs; Circuit theory; Circuits and systems; Discrete Fourier transforms; Electric resistance; Equalizers; Impedance; Lattices; Systolic arrays; Transfer functions; Voltage;
fLanguage :
English
Journal_Title :
Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-4094
Type :
jour
DOI :
10.1109/31.16566
Filename :
16566
Link To Document :
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