• DocumentCode
    1032853
  • Title

    Novel circuit design and implementation of adaptive phase comparators

  • Author

    Haartsen, J.C. ; den Dulk, Richard C.

  • Author_Institution
    Delft University of Technology, Department of Electrical Engineering, Delft, Netherlands
  • Volume
    23
  • Issue
    11
  • fYear
    1987
  • Firstpage
    551
  • Lastpage
    552
  • Abstract
    A novel circuit implementation for an adaptive phasefrequency comparator, which can be conceived of as a 5-cell up-down counter, is proposed. This circuit can handle coincident input signals and has no dead phase zone or intermediate states. These properties greatly improve the performance of a phase-locked loop.
  • Keywords
    digital circuits; phase comparators; phase-locked loops; 5-cell up-down counter; PLL; adaptive phase comparators; adaptive phase-frequency comparator; circuit diagram; coincident input signals; dead zone free; performance; phase-locked loop;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19870395
  • Filename
    4257727
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1032853