A SIMD-systolic architecture and VLSI chip for the two-dimensional DCT and IDCT

Author

Wu, Chen-Mie ; Chiou, Andy

Author_Institution

Dept. of Electron. Eng., Nat. Taiwan Inst. of Technol., Taipei, Taiwan

Volume

39

Issue

4

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

859

Lastpage

869

Abstract

The authors present a SIMD-systolic architecture for computing the two-dimensional discrete cosine transform (2D-DCT) and inverse discrete cosine transform (2D-IDCT). With four processing elements and a dynamic switching network, this architecture can compute 2D-DCT or 2D-IDCT for 8×8 blocks in sixty-four internal clock cycles (or 128 I/O clock cycles). Currently, based on a 0.8 μm SPDM CMOS technology, a forty-pin VLSI chip has been designed and fabricated for such an architecture. Testing results have shown that the chip is functionally correct and can compute 2D-DCT or 2D-IDCT for 8×8 blocks in 8.2 μs

Keywords

CMOS integrated circuits; VLSI; digital arithmetic; discrete cosine transforms; systolic arrays; 0.8 m; 2D IDCT; 2D-DCT; 2D-IDCT; SIMD-systolic architecture; SPDM CMOS technology; VLSI chip; clock cycles; dynamic switching network; inverse discrete cosine transform; processing elements; testing results; two-dimensional DCT; two-dimensional discrete cosine transform; CMOS technology; Clocks; Computer architecture; Computer networks; Discrete cosine transforms; Flow graphs; Image coding; Testing; Transform coding; Very large scale integration;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.267410

Filename

267410