BER Testing of Communication Interfaces

This paper presents a versatile bit-error-rate (BER) testing scheme to characterize the quality of communication interfaces. Traditionally, the presilicon BER is evaluated using time-consuming software simulations. The stand-alone BER test products for postsilicon evaluation are expensive and do not include channel emulators, which are essential to testing the BER under the presence of noise. For both the design and evaluation phases, we present a scheme for BER testing in field-programmable gate arrays (FPGAs) that consists of a BER tester (BERT) core and a novel additive white Gaussian noise (AWGN) generator core. The maximum output value of our AWGN generator is 53, whereas that of the existing solutions is less than 7. Therefore, our generator can better emulate the tail of a Gaussian distribution, which is suitable for exploring applications at very low BERs. We also present a pipelined structure that exploits the central limit theorem for speedups of four or more. Combining a BERT and an AWGN in FPGAs is orders of magnitude more efficient in cost, volume, and energy over the existing similar-speed stand-alone solutions and has a huge speed advantage over software simulations. We demonstrate the applications of our solution through two case studies.