Title :
Hybrid multiplier for GF(2m) defined by some irreducible trinomials
Author :
Choi, Y.J. ; Chang, K.-Y. ; Hong, D.W. ; Cho, H.S.
Author_Institution :
Inf. Security Res. Div., Electron. & Telecommun. Res. Inst., Daejeon, South Korea
fDate :
7/8/2004 12:00:00 AM
Abstract :
A trade-off between performance and area is important to design an efficient hardware structure for arithmetic operations in GF(2m). Proposed is a hybrid multiplier for GF(2m) with an irreducible trinomial, which can be constructed in variable structures depending on such a performance area trade-off.
Keywords :
Galois fields; digital arithmetic; logic design; multiplying circuits; public key cryptography; Galois field hybrid multiplier; arithmetic operations; bit-parallel method; bit-serial method; elliptic curve cryptosystem; hardware implementations; hardware structure; irreducible trinomials; public key cryptosystem;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20040584
