DocumentCode :
1034052
Title :
A power MOSFET design methodology considering epi parameter variations
Author :
Hwang, Seong-Kyu ; Choi, Yearn-Ik ; Chung, Sang-Koo ; Lee, Kwyro ; Kim, Choong-ki
Author_Institution :
Korea Electron. Technol. Inst., Seoul, South Korea
Volume :
6
Issue :
4
fYear :
1993
fDate :
11/1/1993 12:00:00 AM
Firstpage :
377
Lastpage :
380
Abstract :
An optimum design method for power MOSFETs that maximizes the number of good dies is presented. From the device specification of the maximum voltage and current given, the target design value of the breakdown voltage required for the maximum number of good dies it determined by considering the variations of parameters such as thickness and resistivity of the epitaxial layer, chip area, and defect density during the manufacturing process. In the case of a 650-V/5-A power MOSFET, the optimum design target of the breakdown voltage is found to be 710 V, which gives 1213 good dies from a 5-in wafer with the defect density of 5/cm2 when ideal junction termination is assumed. This maximum number of good dies is reduced to 855 in practice due to the nonideal junction termination with 80% of the ideal breakdown voltage, resulting in the target design voltage of 890 V
Keywords :
insulated gate field effect transistors; power transistors; semiconductor epitaxial layers; 5 A; 650 to 890 V; breakdown voltage; chip area; defect density; device specification; epi parameter variations; epitaxial layer; good dies; ideal junction termination; maximum voltage; nonideal junction termination; optimum design method; power MOSFETs; resistivity; target design value; Breakdown voltage; Conductivity; Design methodology; Epitaxial layers; Impurities; MOSFET circuits; Manufacturing processes; Power MOSFET; Semiconductor devices; Surface resistance;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/66.267650
Filename :
267650
Link To Document :
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