DocumentCode :
1034324
Title :
A 32*32-bit multiplier using multiple-valued MOS current-mode circuits
Author :
Kawahito, Shoji ; Kameyama, Michitaka ; Higuchi, Tatsuo ; Yamada, Haruyasu
Author_Institution :
Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan
Volume :
23
Issue :
1
fYear :
1988
Firstpage :
124
Lastpage :
132
Abstract :
A 32*32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2- mu m CMOS technology. For the multiplier based on the radix-4 signed-digit number system, 32*32-bit two´s complement multiplication can be performed with only three-stage signed-digit full adders using a binary-tree addition scheme. The chip contains about 23600 transistors and the effective multiplier size is about 3.2*5.2 mm/sup 2/, which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported.<>
Keywords :
CMOS integrated circuits; digital arithmetic; integrated logic circuits; large scale integration; many-valued logics; multiplying circuits; 2 micron; 59 ns; CMOS technology; LSI; binary-tree addition; many valued logics; multiple-valued current-mode circuits; multiplier; radix-4 signed-digit number system; three-stage signed-digit full adders; two´s complement multiplication; Adders; Arithmetic; CMOS logic circuits; CMOS memory circuits; CMOS technology; Current mode circuits; Large scale integration; Logic devices; Ultra large scale integration; Wiring;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.268
Filename :
268
Link To Document :
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